1. Field
Exemplary embodiments of the present invention relate to semiconductor device fabrication technology, and, more particularly, to a high-voltage MOS transistor.
2. Description of the Related Art
A laterally double-diffused MOS (LDMOS) transistor that is a high voltage MOS transistor is advantageous over a bipolar transistor, because the LDMOS transistor has a high input impedance and power gain, and a circuit for driving the same is very simple. In addition, because the LDMOS transistor is a unipolar device, it is advantageous that the LDMOS transistor is free from the delay caused by minority carrier recombination in a turn-off operation. For these reasons, the LDMOS transistor is widely used in various power devices, including integrated circuits (ICs), power converters, motor controllers and automotive power devices.
FIG. 1 is a cross-sectional view showing a laterally double-diffused MOS (LDMOS) transistor according to the prior art. FIG. 1 illustrates a structure in which two N-channel lateral double-diffused MOS transistors are disposed symmetrically with respect to a bulk pick-up region on a substrate.
Referring to FIG. 1, the N-channel lateral double-diffused MOS transistor according to the prior art includes an N-type deep well 12 formed on a P-type substrate 11, both an N-well 14 and P-well 16 formed in the N-type deep well 12, both an N-type source region 17 and a P-type bulk pick-up region 18 formed in the P-well 16, an N-type drain region 15 formed in the N-type well 14, a gate electrode 20 formed over the substrate 11 between the end of the N-type source region 17 and before the N-type drain region 15, and an insulating layer 21 interposed between the gate electrode 20 and the P-type substrate 11. Herein, the insulating layer 21 includes a gate insulating film 19 and a field oxide film 13.
As it is well known in the art, a process of designing a high-voltage MOS transistor basically requires the minimization of the specific on-resistance (Rsp) of the transistor while maintaining the breakdown voltage (BV) at a high level.
Methods used to increase the breakdown voltage (BV) of the high-voltage MOS transistor in the prior art include reducing the impurity doping concentration of an impurity region (e.g., N-type deep well 12) corresponding to a drift region D, increasing the length of the field oxide film 13 to increase the length of the drift region D, or introducing a P-type impurity layer into the N-type deep well 12 corresponding to the drift region D. For reference, a region in which the gate electrode 20 overlaps with the P-well 16 acts as the channel region C, and a region ranging from the end of the channel region C to the drain region 15 is referred to as the drift region D.
However, the above-described methods inevitably involve an increase in the specific on-resistance (Rsp) of the N-channel lateral double-diffused MOS transistor, thereby reducing the specific on-current of the transistor. On the contrary, to decrease the specific on-resistance of the transistor, when the impurity doping concentration of an impurity region corresponding to the drift region D is increased or the length of the drift region D is reduced, the breakdown voltage (BV) characteristic of the transistor will be deteriorated.
As described above, the breakdown voltage (BV) characteristic and the specific on-resistance (Rsp) characteristic have a trade-off relationship. Thus, there is an urgent need for a method that may sustain both the breakdown voltage (BV) and specific on-resistance (Rsp) characteristics required for a high-voltage MOS transistor.